This invention relates to an essentially zero power circuit which reduces the power consumption of unused circuitry, particularly sense amplifier circuitry used for programmable logic devices (PLD). More specifically, this invention relates to a CMOS power reduction circuit for selectively powering down (i.e., reducing the power consumption of) a sense amplifier for an unused product term of a programmable logic array within a PLD.
Programmable logic devices having programmable logic arrays having input terms and product terms are well known in the art. Moreover, programmable logic arrays using EPROM (erasable, programmable, read only memory) storage cells are well known. The use of these storage cells at the "intersections" of the input terms and product terms allows the electrical programming of each cell. Moreover, these cells may typically be erased by exposing them to ultraviolet light thereby removing the charge from the floating gate which is sandwiched between control electrode of the EPROM device and the channel region of the device. The operation of these programmable logic devices using programmable logic arrays have been described in the literature and in patents. For example, U.S. Pat. Nos. 4,124,899; 4,609,986 and 4,617,479and the references cited in those patents describe such arrays and the operation and construction thereof. This invention has application to various types of programmable logic arrays but is particularly suited to programmable logic arrays using a sum of products where the product of a plurality of input terms is taken on a particular product term which is then summed with other product terms.
As is well known in the art, these programmable logic devices, which utilize programmable logic arrays, allow a system designer to replace many LSI (large scale integration) gates with a single integrated circuit which is referred to as a programmable logic device (PLD). The nature of the PLD, a standard design to replace non-standard logic, requires that it be designed to handle the worst expected logic implementation. This constraint results in the majority of PLD devices being much less than 100% utilized. Consequently, for a particular PLD chip, many product terms are often unused and hence their sense amplifiers draw unnecessary power thereby increasing the overall power consumption of the PLD chip.
Certain attempts have been made in the prior art to reduce the power consumed by PLD's which are not fully utilized. An example of such an attempt is shown in U.S. Pat. No. 4,851,720 , filed Sept. 2, 1988 (entitled: "Low Power Sense Amplifier for Programmable Logic Device") which is assigned to the assignee of the present invention. In that approach, power is reduced by clocking power to the sense amplifiers only when necessary to sense the state of the product terms. That is, power is provided to all sense amplifiers only during a certain period of time designed to coincide with the appearance of valid data on the product terms of the programmable logic devices described in that disclosure. This particular approach requires a synchronous (i.e., clocked) part; moreover, this approach consumes power because the circuits producing the clocking pulses consume power and because all sense amplifiers are turned on whether or not a product term is utilized.
It is an object of the present invention to provide a circuit for selectively disabling unused circuitry, particularly sense amplifiers for unused product terms, in order to reduce power consumption of the unused circuitry. Moreover, it is an object of the present invention to provide a circuit which selectively disables unused circuitry without itself consuming significant power; that is, the circuitry which reduces power is itself a miser at power consumption in both active and stand-by states. Moreover, it is an object of the present invention to provide a power reduction circuit which remembers whether or not the circuitry associated with that power reduction circuit will be provided with power or not provided with power. These and other aspects of the invention will be described below.